Among the problems arising with this type of converter, it has been found that the switching of the transistors at the moment of a change of binary word introduced a significant switching noise. The switching is simultaneous (under the control of a clock) for all the transistors. However, the response times of the different transistors are widely dispersed. Furthermore, the overall response time depends to a significant extent on the difference between two consecutive binary words to be converted. As the frequency F of the clock for timing the digital data elements increases, the linearity of the converter and the spectral purity of the output signal are degraded.
Moreover, the power spectrum of the output signal is limited by the clock frequency used in this switching. This spectrum (the power of the output signal as a function of frequency) is theoretically a curve with multiple lobes in the form of sine (x)/x, having a very high attenuation around the clock frequency, and a peak at a frequency of one and a half times the clock frequency. It is therefore difficult to obtain an output signal at a sufficient level for some frequency ranges, notably around the clock frequency, and it is difficult to obtain an output signal at a level independent of the frequency within the desired frequency range.
There has already been a proposal, in US2006/0022856 for example, for an improvement in which a clock half-period is used to prevent the flow of the current toward the load during the moment when the binary word is switched at the input. The flow of current toward the load is enabled again during the next half-period when the new binary word is well established at the input of the converter.
For example, assuming that the input word is introduced into a buffer register (or “latch”) actuated by a regular clock CLK, CLKb, where CLK represents an active level of the clock during a half-period and CLKb represents a complementary level which is inactive during the next half-period, provision is made to load the buffer register with a new binary word on the falling edge of CLK, to then prevent the flow of current during the half-period CLKb=1 following this falling edge, and to enable the flow of current again during the following half-period CLK=1, the new binary word then being well stabilized. More precisely, the prevention of the flow of current consists in shunting the current away from the resistive loads without interrupting this current in the transistors of the even and odd branches.
Converters of this type are called RTZ converters, that is to say return-to-zero converters, because the analog output signal periodically passes through zero during the half-periods CLKb, where CLK=0.
On the one hand, the spectral purity of the output signal is improved because the suppression of the switching dispersions of the current sources, and on the other hand the spectrum of the output signal is then better distributed and has no troughs in the vicinity of the clock frequency. However, the power of the output signal is lower.
Converters which operate in a complementary way during the two half-periods of the clock frequency have also been proposed. During the first half-period, the transistor currents of the odd differential branches are sent to an odd load and the currents of the even differential branches are sent to the even load. During the next clock half-period, the links between the transistors and the loads are crossed, sending the currents of the odd branches toward the even load and vice versa; thus the converter output signal transmits two successive complementary analog values (the one representing the binary word and the one representing the complementary word) during two successive half-periods of the clock signal. This is, in a manner of speaking, a supplementary modulation of the analog output signal, which is decoded at the time of use. The power of the output signal is, in a manner of speaking, doubled, and the output spectrum is also changed, particularly by reinforcing the power for frequencies located between half the clock frequency and the clock frequency, and even beyond.
Evidently, this switching mode, in which the current from the sources must be sent toward the load during each of the clock half-periods, is incompatible with the RTZ mode, in which the current must be shunted away from the load (toward the power supply) during this half-period.